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課程名稱 |
交換電路與邏輯設計
Switching Circuit and Logic Design |
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開課學期 |
107-1 |
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授課對象 |
電機工程學系 |
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授課教師 |
江蕙如 |
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課號 |
EE2012 |
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課程識別碼 |
901E32300 |
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班次 |
04 |
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學分 |
3.0 |
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全/半年 |
半年 |
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必/選修 |
必修 |
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上課時間 |
星期四8(15:30~16:20)星期五8,9(15:30~17:20) |
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上課地點 |
博理212博理212 |
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備註 |
本課程以英語授課。本系優先。
總人數上限：32人 |
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Ceiba 課程網頁 |
http://ceiba.ntu.edu.tw/1071EE2012_04 |
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課程簡介影片 |
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核心能力關聯 |
核心能力與課程規劃關聯圖 |
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課程大綱
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為確保您我的權利,請尊重智慧財產權及不得非法影印
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課程概述 |
Course contest:
Introduction
- Number Systems and Conversion
Boolean Algebra and its Applications
- Combinational Logic Design and its Minimization
- Karnaugh Maps and Two-Level Logic Minimization
- Multi-Level Gate Circuits
- Combinational Circuit Design
- Multiplexers, Decoders, and Programmable Logic Decices
Sequential Logic Design and its Minimization
- Latches and Flip-Flops
- Registers and Counters
- Analysis of Clock Sequential Circuits
- Derivation of State Graphs and Tables
- Reduction of State Tables
- Sequential Circuit Design
- Circuits for Arithmetic Operations |
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課程目標 |
This course offers an introduction to any undergraduate who wants to understand digital systems. This course is essential for later courses in digital design, design automation, computer organization and architecture, logic synthesis and verification, testing and design for testability. |
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課程要求 |
No prerequisites. |
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預期每週課後學習時數 |
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Office Hours |
每週四 14:00~14:30 備註： by appoitment |
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指定閱讀 |
C. H. Roth, Jr. and L. L. Kinney, Fundamentals of Logic Design, 7th edition, CENGAGE Learning. |
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參考書目 |
待補 |
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評量方式
(僅供參考) |
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No. |
項目 |
百分比 |
說明 |
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1. |
Homework |
14% |
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2. |
Quiz 1 |
4% |
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3. |
Midterm |
35% |
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4. |
Quiz 2 |
4% |
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5. |
Quartus II HW |
6% |
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6. |
Final |
35% |
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7. |
Participation |
2% |
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週次 |
日期 |
單元主題 |
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第1週 |
9/13,9/14 |
Ch. 1. Intro, Number Systems |
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第2週 |
9/20,9/21 |
Ch. 2. Boolean Algebra |
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第3週 |
9/27,9/28 |
Ch. 3. Boolean Algebra (Continued) |
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第4週 |
10/04,10/05 |
Ch. 4. Applications of Boolean Algebra |
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第5週 |
10/11,10/12 |
Ch. 5. Karnaugh Maps /
Ch. 7. Multi-Level Gate Circuits; NAND NOR Gates |
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第6週 |
10/18,10/19 |
Ch. 7. (cont’d) / Quiz 1 (Ch. 1 ~ Ch. 4) / Ch. 7 (cont’d) |
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第7週 |
10/25,10/26 |
Ch. 8. Combinational Ckt Design |
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第8週 |
11/01,11/02 |
Ch. 9. Multiplexers Decoders and PLDs |
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第9週 |
11/08,11/09 |
Review Session / Midterm (Ch. 1 ~ Ch. 9) |
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第10週 |
11/15,11/16 |
11/15 No class (NTU Anniversary) / Combinational Circuit Design using Altera Quartus II |
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第11週 |
11/22,11/23 |
Ch. 11. Latches and FFs / Ch. 12. Registers and Counters |
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第12週 |
11/29,11/30 |
Ch. 12. (cont’d) / Ch. 13. Analysis of Clocked Sequential Ckts |
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第13週 |
12/06,12/07 |
Ch. 13. (cont’d) / Sequential Circuit Design using Altera Quartus II |
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第14週 |
12/13,12/14 |
Ch. 13. (cont’d) / Ch. 14. Derivation of State Graphs and Tables |
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第15週 |
12/20,12/21 |
Ch. 14. (cont’d) / Quiz 2 (Ch. 11 ~ Ch. 13) / Ch 15. Reduction of State Tables |
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第16週 |
12/27,12/28 |
Ch. 15. Reduction of State Tables / Ch. 16. Sequential Ckt Design |
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第17週 |
1/03,1/04 |
Ch. 16. (cont’d) / Supplementary materials |
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第18週 |
1/10,1/11 |
Review Session / Final Exam (Ch. 11 ~ Ch. 16) |
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